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INTEGRATED CIRCUITS
74AVC16836 20-bit registered driver with inverted register enable (3-State)
Preliminary specification
Replaces datasheet 74AVC16836/74AVCH16836 dated 1998 Dec 07
1999 Jul 23
Philips Semiconductors
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
FEATURES
* Wide supply voltage range of 1.2 V to 3.6 V * Complies with JEDEC standard no. 8-1A/5/7. * CMOS low power consumption * Input/output tolerant up to 3.6 V * DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed degradation
PIN CONFIGURATION
OE Y0 Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CP A0 A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 A19 LE
* Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
* Power off disables 74AVC16836 outputs, permitting Live Insertion
DESCRIPTION
The 74AVC16836 is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient. See the graphs on page 8 for typical curves.
Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 Y19 NC
SH00159
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.0 ns; CL = 30 pF. PARAMETER SYMBOL tPHL/tPLH Propagation delay An to Yn Propagation delay LE to Yn; CP to Yn Input capacitance Power dissipation capacitance per buffer dissi ation ca acitance er VI = GND to VCC1 Outputs enabled Output disabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CONDITIONS TYPICAL 2.6 2.0 1.7 3.0 2.4 2.0 5.0 25 6 UNIT ns
tPHL/tPLH CI CPD
ns pF pF F
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II TEMPERATURE RANGE -40C to +85C ORDER CODE 74AVC16836 DGG DRAWING NUMBER SOT364-1
1999 Jul 23
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Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
PIN DESCRIPTION
PIN NUMBER 28 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 4, 11, 18, 25, 32, 35, 39, 46, 53 7, 22, 35, 50 1 29 56 55, 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 SYMBOL NC Y0 to Y19 NAME AND FUNCTION No connection Data outputs
LOGIC SYMBOL (IEEE/IEC)
OE CP LE 1 56 29 C3 G2 EN1 2C3
GND VCC OE LE CP
Ground (0V) Positive supply voltage Output enable input (active LOW) Latch enable input (active LOW) Clock input
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1 1 3D
55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A0 to A19
Data inputs
Y9 Y10 Y11 Y12 Y13 Y14 Y15
LOGIC SYMBOL
OE
Y16 Y17
CP
Y18 Y19
LE
A0
SH00160
D LE CP Y0
FUNCTION TABLE
INPUTS OE H L L L L L L H L X Z = = = = = LE X L L H H H H CP X X X H L A X L H L H X X OUTPUTS Z L H L H Y01 Y02
TO THE 19 OTHER CHANNELS
SH00163
HIGH voltage level LOW voltage level Don't care High impedance "off" state LOW-to-HIGH level transition
NOTES: 1. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. 2. Output level before the indicated steady-state input conditions were established.
1999 Jul 23
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Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
168-pin SDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE AVC16836 AVC16836 AVC16836 PCK2509S or PCK2510S
The PLL clock distribution device and AVC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER DC supply voltage (according to JEDEC Low Voltage Standards) VCC DC supply voltage (for low voltage applications) VI VO Tamb tr, tf DC Input voltage range DC output voltage range; output 3-State DC output voltage range; output HIGH or LOW state Operating free-air temperature range Input rise and fall times VCC = 1.65 to 2.3 V VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V CONDITIONS MIN 1.65 2.3 3.0 1.2 0 0 0 -40 0 0 0 MAX 1.95 2.7 3.6 3.6 3.6 3.6 V VCC +85 30 20 10 C ns/V V UNIT
SDRAM
SW00409
V
1999 Jul 23
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Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER VCC IIK VI IOK VO VO IO IGND, ICC Tstg PTOT DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output 3-State DC output voltage; output HIGH or LOW state DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package -plastic thin-medium-shrink (TSSOP) For temperature range: -40 to +125 C above +55C derate linearly with 8 mW/K VI t0 For all inputs1 VO uVCC or VO t 0 Note 1 Note 1 VO = 0 to VCC CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to 4.6 "50 -0.5 to 4.6 -0.5 to VCC +0.5 "50 "100 -65 to +150 600 UNIT V mA V mA V V mA mA C mW
NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VCC = 1.2 V VIH HIGH level Input voltage In ut VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 1.2 V VIL LOW level In ut voltage Input VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = -100 A VOH HIGH level output voltage VCC = 1.65 V; VI = VIH or VIL; IO = -4 mA VCC = 2.3 V; VI = VIH or VIL; IO = -8 mA VCC = 3.0 V; VI = VIH or VIL; IO = -12 mA VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = 100 A VOL LOW level output voltage VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA II IOFF IIHZ/IILZ IOZ Input leakage current g 3-State output OFF-state current 3-State output OFF-state current VCC = 1.65 to 3.6 V 1 65 3 6 V; VI = VCC or GND VCC = 0 V; VI or VO = 3.6 V VCC = 1.65 to 3.6 V; VI = VCC or GND VCC = 1.65 to 2.7 V; VI = VIH or VIL; VO = VCC or GND VCC = 3.0 to 3.6 V; VI = VIH or VIL; VO = VCC or GND VCC = 1.65 to 2.7 V; VI = VCC or GND; IO = 0 VCC = 3.0 to 3.6 V; VI = VCC or GND; IO = 0 TEST CONDITIONS Temp = -40C to +85C MIN VCC 0.65VCC 1.7 2.0 - - - - VCC*0 20 *0.20 VCC*0.45 VCC*0.55 VCC*0.70 - - - - - - - - - - - TYP1 - 0.9 1.2 1.5 - 0.9 1.2 1.5 VCC VCC*0.10 VCC*0.28 VCC*0.32 GND 0.10 0.26 0.36 0.1 0.1 0.1 0.1 0.1 0.1 0.2 MAX - - - - GND 0.35VCC 0.7 0.8 - - - - 0 20 0.20 0.45 0.55 0.70 2.5 "10 12.5 5 A 10 20 40 A A A A V V V V UNIT
out ut 3-State output OFF-state current
ICC
Quiescent su ly current supply
NOTES: 1. All typical values are at Tamb = 25C. 1999 Jul 23 5
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
AC CHARACTERISTICS
GND = 0 V; tr = tf 2.0 ns; CL = 30 pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3 0.3 V MIN Propagation delay An to Yn tPHL/tPLH Propagation delay LE to Yn Propagation delay CP to Yn tPZH/tPZL tPHZ/tPLZ 3-State output enable time OE to Yn 3-State output disable time OE to Yn CP pulse width HIGH or LOW LE pulse width HIGH Set-up time An to CP tS SU Set-up time An to LE Hold time An to CP th Fmax Hold time An to LE Maximum clock pulse frequency 1, 7 2, 7 3, 7 6, 7 6, 7 3, 7 2, 7 5, 7 4, 7 5, 7 4, 7 3, 7 0.7 0.7 0.7 1.0 1.0 1.0 1.0 0.3 0.3 0.3 0.3 500 TYP1 1.7 2.0 1.9 2.5 2.5 - - - - - - - MAX 2.5 3.0 2.9 4.5 4.0 - - - - - - - VCC = 2.5 0.2 V MIN 0.8 0.8 0.8 1.0 1.0 1.2 1.2 0.4 0.4 0.4 0.4 400 TYP1 2.0 2.4 2.2 2.8 2.4 - - - - - - - MAX 3.0 3.6 3.3 5.0 4.5 - - - - - - - VCC = 1.8 0.15 V MIN 1.0 1.0 0.9 1.5 1.5 2.0 2.0 0.5 0.5 0.5 0.5 250 TYP1 2.6 3.0 2.8 3.5 4.0 - - - - - - - MAX 4.5 5.5 5.2 6.5 6.5 - - - - - ns - - MHz VCC = 1.2 V TYP 5.2 6.0 5.5 6.0 6.0 - ns - - ns - ns ns ns UNIT
tW
NOTES: 1. All typical values are measured at Tamb = 25C and at VCC = 1.8 V, 2.5 V, 3.3 V.
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE
VM = 0.5 VCC VX = VOL + 0.300 V VY = VOH - 0.300 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC
VI LE INPUT GND VM tW VM
tPHL
VOH Yn OUTPUT VOL VM
tPLH
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND VCC < 2.3 V RANGE
VM = 0.5 VCC VX = VOL + 0.15 V VY = VOH - 0.15 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC
VI An INPUT GND tPHL VOH Yn OUTPUT VOL NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V VM tPLH VM
NOTE: VM = 0.5 VCC at VCC = 2.3 to 2.7 V
SH00165
Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Yn) propagation delays.
SH00132
Waveform 1. Input (An) to output (Yn) propagation delay 1999 Jul 23 6
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE (Continued)
VM = 0.5 VCC VX = VOL + 0.300 V VY = VOH - 0.300 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC
VI CP INPUT GND tsu th VI An INPUT GND VOH Yn OUTPUT VOL tsu th VM
VM = 0.5 VCC VX = VOL + 0.15 V VY = VOH - 0.15 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC
1/fMAX VI CP INPUT GND VM tW VM
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00136
Waveform 5. Data set-up and hold times for the An input to the clock CP input
tPHL
VOH Yn OUTPUT VOL VM
tPLH
VI nOE INPUT GND VM
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00135
Waveform 3. The clock (CP) to Yn propagation delays, the clock pulse width and the maximum clock frequency.
VCC OUTPUT LOW-to-OFF OFF-to-LOW
VI An INPUT
VM
VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V outputs disabled outputs enabled VY VM tPZH
GND
th
th
tSU
tSU
VI LE INPUT
VM
GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00166
Waveform 4. Data set-up and hold times for the An input to the LE input
Waveform 6. 3-State enable and disable times
1999 Jul 23
7
EEE E EEEEEEEEEEEE EE EEEEEEEEEEEE EEEEEEEEEEE E
VM tPLZ tPZL VM VX
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND VCC < 2.3V RANGE (Continued)
EEEEEEEEE EEE E EEEEEEEEE EEE E EEEEEEEEE EEE E
SH00137
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
TEST CIRCUIT
VCC S1 2 * VCC Open GND
GRAPHS
0 I OH (mA) OUTPUT CURRENT -50 -100 -150 -200 -250 3.3V -300 -350 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH (V) OUTPUT VOLTAGE PMOS 2.5V 1.8V
VI PULSE GENERATOR RT D.U.T.
VO
RL
CL
RL
Test Circuit for switching times DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SH00161
SWITCH POSITION
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 < VCC
GND
VCC < 2.3 V 2.3-2.7 V 3.0 V
VI VCC VCC VCC
RL 1000 500 500 I OH (mA) OUTPUT CURRENT
-350 -300 -250 3.3V -200 -150 2.5V -100 -50 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH (V) OUTPUT VOLTAGE 1.8V NMOS
SV01018
Waveform 7. Load circuitry for switching times
SH00162
1999 Jul 23
8
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1999 Jul 23
9
Philips Semiconductors
Preliminary specification
20-bit registered driver with inverted register enable (3-State)
74AVC16836
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 07-99 9397-750-06252
Philips Semiconductors
1999 Jul 23 10

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